The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a capacitor in a semiconductor device.
As semiconductor devices such as DRAM become highly integrated, the unit cell size and operating voltage decrease. Thus, the device refresh time is often shortened, and a soft error can frequently occur. To overcome these limitations, capacitors need to be developed to have a capacitance of 25 fF per cell or higher and a reduced leakage current.
Generally, a capacitor formed in a structure of nitride and oxide (NO) using Si3N4 as a dielectric material is disadvantageous in capacitance when it comes to large scale integration. There is not enough area to obtain the required capacitance. Instead of using Si3N4, a capacitor structure that uses a high-K dielectric material (e.g., tantalum oxide (Ta2O5), lanthanum oxide (La2O3) or hafnium oxide (HfO2)) in a single dielectric layer is developed to obtain sufficient capacitance. This particular capacitor structure is called a polysilicon-insulator-polysilicon (SIS) structure.
However, a SIS capacitor structure using an Al2O3 dielectric material may have capacitance limitations in 512M level or higher dynamic random access memories (DRAMs). Thus, many researchers are focused on developing other capacitor structures, such as a metal-insulator-metal (MIM) structure using a titanium nitride (TiN) electrode and an HfO2/Al2O3 or HfO2/Al2O3/HfO2 dielectric structure.
When the aforementioned capacitor structure is used, the expected equivalent oxide thickness (Tox) is about 12 Å. To increase capacitance without reducing oxide thickness, capacitor area can be increased with a 3D electrode structure. In DRAM products with sub-70 nm level metal interconnection technology, obtaining cell capacitance of about 25 fF/cell or higher may result in a complex bottom electrode structure. Accordingly, it may be difficult to obtain the desired capacitance if the area of the bottom electrode structure is not enlarged.
Recently, many studies on MIM capacitor structures have made progress. These MIM capacitor structures use a noble metal, e.g., ruthenium (Ru), as an electrode material and Ta2O5 or HfO2 as a single dielectric material.
However, if the equivalent oxide thickness is decreased to about 12 Å or less along with using the Ru electrode, the MIM capacitor is likely to have a high leakage current; about 1 fA per cell in some instances. Accordingly, it may be difficult to implement this MIM capacitor in DRAM with 512M or higher capacity that uses sub-70 nm level interconnection technology.